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- Wiley
More About This Title ESD - Analog Circuits and Design
English
A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design
This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect presents the additional challenges associated with the design of adequate and effective ESD protection elements and schemes. A comprehensive list of practical application examples is used to demonstrate the successful combination of both techniques and any potential design trade-offs.
Chapter One looks at analog design discipline, including layout and analog matching and analog layout design practices. Chapter Two discusses analog design with circuits, examining: single transistor amplifiers; multi-transistor amplifiers; active loads and more. The third chapter covers analog design layout (also MOSFET layout), before Chapters Four and Five discuss analog design synthesis. The next chapters introduce the reader to analog-digital mixed signal design synthesis, analog signal pin ESD networks, and analog ESD power clamps. Chapter Nine, the last chapter, covers ESD design in analog applications.
- Clearly describes analog design fundamentals (circuit fundamentals) as well as outlining the various ESD implications
- Covers a large breadth of subjects and technologies, such as CMOS, LDMOS, BCD, SOI, and thick body SOI
- Establishes an “ESD analog design” discipline that distinguishes itself from the alternative ESD digital design focus
- Focuses on circuit and circuit design applications
- Assessible, with the artwork and tutorial style of the ESD book series
- PowerPoint slides are available for university faculty members
Even in the world of digital circuits, analog and power circuits are two very important but under-addressed topics, especially from the ESD aspect. Dr. Voldman’s new book will serve as an essential and practical guide to the greater IC community. With high practical and academic values this book is a “bible” for professionals, graduate students, device and circuit designers for investigating the physics of ESD and for product designs and testing.
English
English
Preface xix
Acknowledgments xxiii
1 Analog, ESD, and EOS 1
1.1 ESD in Analog Design 1
1.2 Analog Design Discipline and ESD Circuit Techniques 2
1.2.1 Analog Design: Local Matching 3
1.2.2 Analog Design: Global Matching 3
1.2.3 Symmetry 3
1.2.3.1 Layout Symmetry 4
1.2.3.2 Thermal Symmetry 4
1.2.4 Analog Design: Across Chip Linewidth Variation 4
1.3 Design Symmetry and ESD 5
1.4 ESD Design Synthesis and Architecture Flow 6
1.5 ESD Design and Noise 7
1.6 ESD Design Concepts: Adjacency 8
1.7 Electrical Overstress 8
1.7.1 Electrical Overcurrent 10
1.7.2 Electrical Overvoltage 11
1.7.3 Electrical Overstress Events 11
1.7.3.1 Characteristic Time Response 11
1.7.4 Comparison of EOS versus ESD Waveforms 13
1.8 Reliability Technology Scaling and the Reliability Bathtub Curve 13
1.8.1 The Shrinking Reliability Design Box 14
1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage 14
1.9 Safe Operating Area 15
1.9.1 Electrical Safe Operating Area 16
1.9.2 Thermal Safe Operating Area (T-SOA) 16
1.9.3 Transient Safe Operating Area 16
1.10 Closing Comments and Summary 17
References 18
2 Analog Design Layout 19
2.1 Analog Design Layout Revisited 19
2.1.1 Analog Design: Local Matching 20
2.1.2 Analog Design: Global Matching 21
2.1.3 Symmetry 21
2.1.4 Layout Design Symmetry 21
2.1.5 Thermal Symmetry 22
2.2 Common Centroid Design 22
2.2.1 Common Centroid Arrays 22
2.2.2 One-Axis Common Centroid Design 22
2.2.3 Two-Axis Common Centroid Design 23
2.3 Interdigitation Design 24
2.4 Common Centroid and Interdigitation Design 24
2.5 Passive Element Design 25
2.6 Resistor Element Design 25
2.6.1 Resistor Element Design: Dogbone Layout 25
2.6.2 Resistor Design: Analog Interdigitated Layout 26
2.6.3 Dummy Resistor Layout 26
2.6.4 Thermoelectric Cancellation Layout 27
2.6.5 Electrostatic Shield 28
2.6.6 Interdigitated Resistors and ESD Parasitics 28
2.7 Capacitor Element Design 29
2.8 Inductor Element Design 30
2.9 Diode Design 33
2.10 MOSFET Design 35
2.11 Bipolar Transistor Design 36
2.12 Closing Comments and Summary 36
References 37
3 Analog Design Circuits 39
3.1 Analog Circuits 39
3.2 Single-Ended Receivers 40
3.2.1 Single-Ended Receivers 40
3.2.2 Schmitt Trigger Receivers 41
3.3 Differential Receivers 41
3.4 Comparators 43
3.5 Current Sources 43
3.6 Current Mirrors 44
3.6.1 Widlar Current Mirror 44
3.6.2 Wilson Current Mirror 45
3.7 Voltage Regulators 46
3.7.1 Buck Converters 46
3.7.2 Boost Converters 46
3.7.3 Buck–Boost Converters 47
3.7.4 Cuk Converters 48
3.8 Voltage Reference Circuits 49
3.8.1 Brokaw Bandgap Voltage Reference 49
3.9 Converters 49
3.9.1 Analog-to-Digital Converter 50
3.9.2 Digital-to-Analog Converters 50
3.10 Oscillators 50
3.11 Phase Lock Loop 50
3.12 Delay Locked Loop 50
3.13 Closing Comments and Summary 52
References 52
4 Analog ESD Circuits 55
4.1 Analog ESD Devices and Circuits 55
4.2 ESD Diodes 55
4.2.1 Dual Diode and Series Diodes 55
4.2.2 Dual Diode–Resistor 56
4.2.3 Dual Diode–Resistor–Dual Diode 56
4.2.4 Dual Diode–Resistor–Grounded-Gate MOSFET 58
4.2.5 Back-to-Back Diode Strings 58
4.2.5.1 Back-to-Back Symmetric Diode String 59
4.2.5.2 Back-to-Back Asymmetric Diode String 59
4.3 ESD MOSFET Circuits 59
4.3.1 Grounded-Gate MOSFET 60
4.3.2 RC-Triggered MOSFET 61
4.4 ESD Silicon-Controlled Rectifier Circuits 62
4.4.1 Unidirectional SCR 62
4.4.2 Bidirectional SCR 62
4.4.3 Medium-Level Silicon-Controlled Rectifier 62
4.4.4 Low-Voltage-Triggered SCR 64
4.5 Laterally Diffused MOS Circuits 64
4.5.1 LOCOS-Defined LDMOS 65
4.5.2 STI-Defined LDMOS 66
4.5.3 STI-Defined Isolated LDMOS 66
4.6 DeMOS Circuits 68
4.6.1 DeNMOS 68
4.6.2 DeNMOS-SCR 69
4.7 Ultrahigh-Voltage LDMOS Circuits 69
4.7.1 Ultrahigh-Voltage LDMOS 70
4.7.2 Ultrahigh-Voltage LDMOS SCR 71
4.8 Closing Comments and Summary 72
References 72
5 Analog and ESD Design Synthesis 73
5.1 Early ESD Failures in Analog Design 73
5.2 Mixed-Voltage Interface: Voltage Regulator Failures 73
5.2.1 ESD Protection Solution for Voltage Regulator: GGNMOS ESD Bypass between Power Rails 75
5.2.2 ESD Protection Solution for Voltage Regulator: Series Diode String ESD Bypass 76
5.3 Separation of Analog Power from Digital Power AVDD to DVDD 76
5.4 ESD Failure in Phase Lock Loop (PLL) and System Clock 77
5.5 ESD Failure in Current Mirrors 77
5.6 ESD Failure in Schmitt Trigger Receivers 78
5.7 Isolated Digital and Analog Domains 82
5.8 ESD Protection Solution: Connectivity of AVDD to VDD 82
5.9 Connectivity of AVSS to DVSS 83
5.10 Digital and Analog Domain with ESD Power Clamps 84
5.11 Digital and Analog Domain with Master/Slave ESD Power Clamps 86
5.12 High-Voltage, Digital, and Analog Domain Floor Plan 87
5.13 Closing Comments and Summary 88
References 88
6 Analog-to-Digital ESD Design Synthesis 89
6.1 Digital and Analog 89
6.2 Interdomain Signal Line ESD Failures 90
6.2.1 Digital-to-Analog Signal Line Failures 90
6.3 Digital-to-Analog Core Spatial Isolation 92
6.4 Digital-to-Analog Core Ground Coupling 92
6.4.1 Digital-to-Analog Core Resistive Ground Coupling 93
6.4.2 Digital-to-Analog Core Diode Ground Coupling 93
6.5 Domain-to-Domain Signal Line ESD Networks 94
6.6 Domain-to-Domain Third-Party Coupling Networks 94
6.7 Domain-to-Domain Cross-Domain ESD Power Clamp 95
6.8 Digital-to-Analog Domain Moat 96
6.9 Digital-to-Analog Domain Moat with Through-Silicon Via 96
6.10 Domain-to-Domain ESD Design Rule Check and Verification Methods 97
6.11 Closing Comments and Summary 97
References 97
7 Analog-ESD Signal Pin Co-synthesis 101
7.1 Analog Signal Pin 101
7.2 Analog Signal Differential Receiver 102
7.2.1 Analog Signal CMOS Differential Receivers 102
7.2.2 Analog Signal Bipolar Differential Receivers 104
7.3 Analog CMOS Differential Receiver 108
7.3.1 Analog Differential Receiver Capacitance Loading 108
7.3.2 Analog Differential Receiver ESD Mismatch 109
7.4 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout 110
7.5 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements 113
7.6 Closing Comments and Summary 115
References 116
8 Analog and ESD Circuit Integration 119
8.1 Analog and Power Technology and ESD Circuit Integration 119
8.1.1 Analog ESD: Isolated and Nonisolated Designs 119
8.1.2 Integrated Body Ties 119
8.1.3 Self-Protecting versus Non-Self-Protecting Designs 120
8.2 ESD Input Circuits 120
8.2.1 Analog Input Circuit Protection 120
8.2.2 High-Voltage Analog Input Circuit Protection 120
8.2.3 Analog Input High-Voltage Grounded-Gate NMOS (GGNMOS) 121
8.2.4 Two-Stage High-Voltage Analog Input Circuit Protection 122
8.3 Analog ESD Output Circuits 123
8.3.1 Analog ESD Output Networks and Distinctions 123
8.3.2 Analog Open-Drain ESD Output Networks 123
8.4 Analog ESD Ground-to-Ground Networks 124
8.4.1 Back-to-Back CMOS Diode String 125
8.4.2 HV GGNMOS Diode-Configured Ground-to-Ground Network 125
8.5 ESD Power Clamps 125
8.5.1 ESD Power Clamp Issues for the High-Voltage Domain 125
8.5.2 HV Domain ESD Protection and ABS MAX 126
8.5.3 HV Domain VIN or VCC Input 126
8.5.4 HV Grounded-Gate NMOS (GGNMOS) 126
8.5.5 HV Series Cascode ESD Network 127
8.5.6 ESD Power Clamp Bidirectionality and Return Diodes 128
8.5.7 Alternative Solutions: LDO Current Limits 128
8.5.8 Alternative Solutions: External EOS Diode 129
8.6 ESD Power Clamps for Low-Voltage Digital and Analog Domain 129
8.6.1 Classification of ESD Power Clamps 130
8.6.2 ESD Power Clamp: Key Design Parameters 131
8.6.3 Design Synthesis of ESD Power Clamps 132
8.6.4 Transient Response Frequency Trigger Element and the ESD Frequency Window 132
8.6.5 ESD Power Clamp Frequency Design Window 133
8.6.6 Design Synthesis of ESD Power Clamp: Voltage-Triggered ESD Trigger Elements 133
8.6.7 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 135
8.6.8 ESD Power Clamp Trigger Condition versus Shunt Failure 136
8.6.9 ESD Clamp Element: Width Scaling 136
8.6.10 ESD Clamp Element: On-Resistance 136
8.6.11 ESD Clamp Element: Safe Operating Area 137
8.7 ESD Power Clamp Issues 137
8.7.1 Power-Up and Power-Down 137
8.7.2 False Triggering 137
8.7.3 Precharging 138
8.7.4 Postcharging 138
8.8 ESD Power Clamp Design 138
8.8.1 Native Power Supply RC-Triggered MOSFET ESD Power Clamp 138
8.8.2 Nonnative Power Supply RC-Triggered MOSFET ESD Power Clamp 139
8.8.3 ESD Power Clamp Networks with Improved Inverter Stage Feedback 140
8.8.4 Forward-Bias Triggered ESD Power Clamps 141
8.8.5 IEC 61000-4-2 Responsive ESD Power Clamps 142
8.8.6 Precharging and Postcharging Insensitive ESD Power Clamps 142
8.8.7 ESD Power Clamp Design Synthesis and Return Diode 143
8.9 Bipolar ESD Power Clamps 144
8.9.1 Bipolar ESD Power Clamps with Zener Breakdown Trigger Element 144
8.9.2 Bipolar ESD Power Clamps with Bipolar Transistor BVCEO Breakdown Trigger Element 145
8.10 Closing Comments and Summary 145
References 146
9 System-Level EOS Issues for Analog Design 147
9.1 EOS Protection Devices 147
9.1.1 EOS Protection Device: Voltage Suppression Devices 147
9.1.2 EOS Protection Device: Current-Limiting Devices 148
9.2 EOS Protection Device: Directionality 150
9.2.1 Classification: I–V Characteristic Type 150
9.2.2 Unidirectionality 150
9.2.3 Bidirectionality 150
9.3 System-Level Pulse Model 152
9.3.1 IEC 61000-4-2 System-Level Pulse Model 152
9.3.2 Human Metal Model (HMM) 152
9.3.3 IEC 61000-4-5 Surge Test 154
9.4 EOS Transient Voltage Suppression (TVS) 155
9.4.1 EOS Diodes 155
9.4.2 EOS Schottky Diodes 156
9.4.3 EOS Zener Diodes 156
9.4.4 EOS Thyristor Surge Protection 157
9.4.5 EOS Metal-Oxide Varistors (MOV) 157
9.4.6 EOS Gas Discharge Tubes (GDT) 159
9.5 EOS Current Suppression Devices 161
9.5.1 EOS PTC Device 161
9.5.2 EOS Conductive Polymer 162
9.5.3 EOS Fuses 163
9.5.3.1 Rated Current IN 164
9.5.3.2 Speed 164
9.5.3.3 I 2t Value 164
9.5.3.4 Breaking Capacity 164
9.5.3.5 Rated Voltage 164
9.5.3.6 Voltage Drop 164
9.5.3.7 Temperature Derating 164
9.5.4 EOS eFUSEs 165
9.5.5 Circuit Breakers 166
9.6 EOS and EMI Prevention: Printed Circuit Board Design 166
9.6.1 Printed Circuit Board Power Plane and Ground Design 167
9.6.2 Printed Circuit Board Design Guidelines: Component Selection and Placement 168
9.6.3 Printed Circuit Board Design Guidelines: Trace Routing and Planes 168
9.6.4 Printed Circuit Board Card Insertion Contacts 170
9.6.5 System-Level Printed Circuit Board: Ground Design 170
9.7 Closing Comments and Summary 171
References 171
10 Latchup Issues for Analog Design 173
10.1 Latchup in Analog Applications 173
10.2 I/O-to-I/O Latchup 173
10.3 I/O-to-I/O Latchup: N-Well to N-Well 175
10.4 I/O-to-I/O Latchup: N-Well to NFET 177
10.5 I/O-to-I/O Latchup: NFET to NFET 179
10.6 I/O-to-I/O Latchup: N-Well Guard Ring between Adjacent Cells 180
10.7 Latchup of Analog I/O to Adjacent Structures 181
10.7.1 Latchup in Core-Dominated Semiconductor Chips 181
10.7.2 Latchup and Grounded N-Wells 181
10.7.3 Latchup and Decoupling Capacitors 181
10.7.4 Adjacency Design Rule Checking and Verification 181
10.8 Analog I/O to Core 182
10.9 Core-to-Core Analog–Digital Floor Planning 182
10.9.1 Analog–Digital Moats and Guard Rings 183
10.10 High-Voltage Guard Rings 184
10.11 Through-Silicon Via (TSV) 185
10.12 Trench Guard Rings 186
10.13 Active Guard Rings 187
10.14 Closing Comments and Summary 190
References 191
11 Analog ESD Library and Documents 195
11.1 Analog Design Library 195
11.2 Analog Device Library: Passive Elements 195
11.2.1 Resistors 196
11.2.2 Capacitors 196
11.2.3 Inductors 197
11.3 Analog Device Library: Active Elements 197
11.4 Analog Design Library: Repository of Analog Circuits and Cores 198
11.4.1 Analog Design Library: Reuse Library 198
11.5 ESD Device Library 198
11.6 Cadence-Based Parameterized Cells (PCells) 199
11.6.1 ESD Hierarchical PCell Physical Layout Generation 200
11.6.2 ESD Hierarchical PCell Schematic Generation 201
11.6.3 ESD Design with Hierarchical Parameterized Cells 201
11.6.4 Hierarchical PCell Graphical Method 202
11.6.5 Hierarchical PCell Schematic Method 204
11.7 Analog ESD Documents 208
11.7.1 ESD Technology Design Manual Section 208
11.7.1.1 ESD Required Specifications 209
11.7.1.2 ESD Supported Standards 209
11.7.1.2.1 Human Body Model (HBM) 209
11.7.1.2.2 Machine Model (MM) 209
11.7.1.2.3 Charged Device Model (CDM) 209
11.7.1.2.4 IEC 61000-4-2 210
11.7.1.2.5 Human Metal Model (HMM) 210
11.7.1.2.6 Transmission Line Pulse (TLP) 210
11.7.1.2.7 Very Fast Transmission Line Pulse (VF-TLP) 210
11.7.1.3 ESD Supported Designs 210
11.7.1.4 ESD Design Rules 210
11.7.1.5 ESD Design Recommendations 211
11.7.1.6 ESD Guard Ring Rules 211
11.7.1.7 ESD Layout Design Practices 211
11.7.1.8 Do’s and Don’ts 211
11.8 ESD Cookbook 212
11.9 Electrical Overstress (EOS) Documents 213
11.9.1 EOS Design Release Process 214
11.9.2 Electrical Overstress (EOS) Cookbook 214
11.9.2.1 Table of Pin Types 216
11.9.3 Electrical Overstress Checklist 218
11.9.4 Electrical Overstress Design Reviews 220
11.10 Closing Comments and Summary 220
References 220
12 Analog ESD and Latchup Design Rule Checking and Verification 223
12.1 Electronic Design Automation 223
12.2 Electrical Overstress (EOS) and ESD Design Rule Checking 223
12.2.1 ESD Design Rule Checking 224
12.2.2 Electrostatic Discharge Layout-versus-Schematic Verification 225
12.2.3 ESD Electrical Rule Check (ERC) 226
12.3 Electrical Overstress (EOS) Electronic Design Automation 227
12.3.1 Electrical Overstress (EOS) Design Rule Checking 227
12.3.2 Electrical Overstress (EOS) Layout-versus-Schematic (LVS) Verification 228
12.3.3 Electrical Overstress (EOS) Electrical Rule Check (ERC) 229
12.3.4 Electrical Overstress Programmable Electrical Rule Check 230
12.4 Printed Circuit Board (PCB) Design Rule Checking and Verification 230
12.5 Electrical Overstress and Latchup Design Rule Checking (DRC) 232
12.5.1 Latchup Design Rule Checking 232
12.5.2 Latchup Electrical Rule Check (ERC) 237
12.5.2.1 N-Well Contact to P-Channel MOSFET Resistance 237
12.5.2.2 P-Well or P-Substrate Contact to N-Channel MOSFET Resistance 237
12.5.2.3 Guard Ring Resistance 237
12.6 Whole-Chip Checking and Verification Methods 240
12.7 Cross-Domain Signal Line Checking and Verification 241
12.7.1 Cross-Domain Signal Line Checking and Verification Flow System 241
12.7.2 Cross-Domain Analog Signal Line Checking and Verification Flow System 243
12.7.3 Cross-Domain Checking and Verification: Resistance Extraction Methodology 244
12.8 Closing Comments and Summary 246
References 246
Appendix: Standards 251
Appendix: Glossary of Terms 255
Index 261
