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More About This Title Physics and Technology of Crystalline OxideSemiconductor CAAC-IGZO - Application to LSI
English
Key features:
• Outlines the physics and characteristics of CAAC-IGZO FETs that contribute to favorable operations of LSI devices.
• Explains the application of CAAC-IGZO to LSI devices, highlighting attributes including low off-state current, low power consumption, and excellent charge retention.
• Describes the NOSRAM, DOSRAM, CPU, FPGA, image sensors, and etc., referring to prototype chips fabricated by a hybrid process of CAAC-IGZO and Si FETs.
English
Dr. Shunpei Yamazaki is an authority on semiconductors, memory devices, and liquid crystal displays. Listed on over 4,000 US utility patents, Dr. Yamazaki was named in the Guinness Book of World Records as holding the most patents in the world; hailed the most prolific inventor in history by USA Today (in 2005). His most notable work is on the thin-film transistor -- a significant discovery being a crystalline structure in Indium gallium zinc oxide (IGZO) material, which he discovered "by chance" in 2009. Today Dr. Yamazaki is President of the Semiconductor Energy Laboratory (SEL), where he and his team pioneered the unique development of ultra-low-power devices using CAAC-IGZO technology. A joint venture with the Sharp Corporation manufacturing smartphones using crystalline oxide semiconductors (IGZO) is a global first. In 2015 Dr. Yamazaki received the SID (Society for Information Display) Special Recognition Award for "discovering CAAC-IGZO semiconductors, leading its practical application, and paving the way to next-generation displays." His paper on CAAC-IGZO ranked in the top 15 most downloaded papers of Wiley Electrical Engineering and Communications Technology journals, 2014. Dr. Yamazaki is also an IEEE Life Fellow.
Masahiro Fujita, University of Tokyo, Japan
Masahiro Fujita: received his Ph.D. in Information Engineering from the University of Tokyo in 1985 on his work on model checking of hardware designs by using logic programming languages. In 1985, he joined Fujitsu as a researcher and started to work on hardware automatic synthesis as well as formal verification methods and tools. From 1993 to 2000, he was director at Fujitsu Laboratories of America and headed a hardware formal verification group developing a formal verifier for real-life designs. Since March 2000, he has been a professor at VLSI Design and Education Center of the University of Tokyo. He has authored and co-authored more than 10 books and 300 publications, and has been given several awards from scientific societies. His research interests include synthesis and verification of hardware and software systems.
English
About the Editors x
List of Contributors xii
Series Editor’s Foreword xiii
Preface xv
Acknowledgments xviii
1 Introduction 1
1.1 Overview of this Book 1
1.2 Background 3
1.2.1 Typical Characteristics of CAAC-IGZO FETs 3
1.2.2 Possible Applications of CAAC-IGZO FETs 4
1.3 Summary of Each Chapter 7
References 9
2 Device Physics of CAAC-IGZO FET 11
2.1 Introduction 11
2.2 Off-State Current 14
2.2.1 Off-State Current Comparison between Si and CAAC-IGZO FETs 14
2.2.2 Measurement of Extremely Low Off-State Current 16
2.2.3 Theoretical Discussion with Energy Band Diagram 23
2.2.4 Conclusion 28
2.3 Subthreshold Characteristics 29
2.3.1 Estimation of Icut by SS 30
2.3.2 Extraction Method of Interface Levels 33
2.3.3 Reproduction of Measured Value and Estimation of Icut 35
2.3.4 Conclusion 38
2.4 Technique for Controlling Threshold Voltage (Vth) 39
2.4.1 Vth Control by Application of Back-Gate Bias 39
2.4.2 Vth Control by Formation of Circuit for Retaining Back-Gate Bias 42
2.4.3 Vth Control by Charge Injection into the Charge Trap Layer 45
2.4.4 Conclusion 49
2.5 On-State Characteristics 49
2.5.1 Channel-Length Dependence of Field-Effect Mobility 50
2.5.2 Measurement of Cut-off Frequency 59
2.5.3 Summary 62
2.6 Short-Channel Effect 62
2.6.1 Features of S-ch CAAC-IGZO FETs 63
2.6.2 Effect of S-ch Structure 70
2.6.3 Intrinsic Accumulation-Mode Device 71
2.6.4 Dielectric Anisotropy 74
2.6.5 Numerical Calculation of the Band Diagrams in IGZO FETs 76
2.6.6 Summary 82
2.7 20-nm-Node CAAC-IGZO FET 83
2.7.1 TGSA CAAC-IGZO FET 83
2.7.2 Device Characteristics 86
2.7.3 Memory-Retention Characteristics 89
2.7.4 Summary 92
2.8 Hybrid Structure 92
2.8.1 TGTC Structure 93
2.8.2 TGSA Structure 94
2.8.3 Hybrid Structure 96
Appendix: Comparison between CAAC-IGZO and Si 98
References 99
3 NOSRAM 102
3.1 Introduction 102
3.2 Memory Characteristics 103
3.3 Application of CAAC-IGZO FETs to Memory and their Operation 104
3.4 Configuration and Operation of NOSRAM Module 106
3.4.1 NOSRAM Module 106
3.4.2 Setting Operational Voltage of NOSRAM Module 106
3.4.3 Operation of NOSRAM Module 108
3.5 Multilevel NOSRAM 108
3.5.1 4-Level (2 Bits/Cell) NOSRAM Module 110
3.5.2 8-Level (3 Bits/Cell) NOSRAM Module 112
3.5.3 16-Level (4 Bits/Cell) NOSRAM Module 114
3.5.4 Stacked Multilevel NOSRAM 119
3.6 Prototype and Characterization 120
3.6.1 2-Level NOSRAM 120
3.6.2 4-Level NOSRAM 128
3.6.3 8-Level NOSRAM 128
3.6.4 16-Level NOSRAM 129
3.6.5 Comparison of Prototypes 133
References 136
4 DOSRAM 137
4.1 Introduction 137
4.2 Characteristics and Problems of DRAM 138
4.3 Operations and Characteristics of DOSRAM Memory Cell 138
4.4 Configuration and Basic Operation of DOSRAM 139
4.4.1 Circuit Configuration and Operation of DOSRAM 139
4.4.2 Hybrid Structure of DOSRAM 139
4.5 Operation of Sense Amplifier 140
4.5.1 Writing Operation 140
4.5.2 Reading Operation 141
4.6 Characteristic Measurement 143
4.6.1 Writing Characteristics 143
4.6.2 Reading Characteristics 144
4.6.3 Data-Retention Characteristics 145
4.6.4 Summary of 8-kbit DOSRAM 146
4.7 Prototype DOSRAM Using 60-nm Technology Node 147
4.7.1 Configuration of Prototype 147
4.7.2 Measurements of Prototype Characteristics 148
4.7.3 Summary for Prototype DOSRAM 151
4.8 Conclusion 151
References 152
5 CPU 153
5.1 Introduction 153
5.2 Normally-Off Computing 153
5.3 CPUs 156
5.3.1 Flip-Flop (FF) 158
5.3.2 8-Bit Normally-Off CPU 166
5.3.3 32-Bit Normally-Off CPU (MIPS-Like CPU) 170
5.3.4 32-Bit Normally-Off CPU (ARM® Cortex®-M0) 174
5.4 CAAC-IGZO Cache Memory 181
References 192
6 FPGA 194
6.1 Introduction 194
6.2 CAAC-IGZO FPGA 195
6.2.1 Overview 195
6.2.2 PRS 197
6.2.3 PLE 200
6.2.4 Prototype 202
6.3 Multicontext FPGA Realizing Fine-Grained Power Gating 209
6.3.1 Overview 209
6.3.2 Normally-Off Computing 209
6.3.3 Prototype 216
6.4 Subthreshold Operation of FPGA 226
6.4.1 Overview 226
6.4.2 Subthreshold Operation 227
6.4.3 Prototype 234
6.5 CPU + FPGA 240
6.5.1 Overview 240
6.5.2 CPU Computing 241
6.5.3 CPU + GPU Computing 242
6.5.4 CPU + FPGA Computing 243
6.5.5 CAAC-IGZO CPU + CAAC-IGZO FPGA Computing 246
References 247
7 Image Sensor 250
7.1 Introduction 250
7.2 Global Shutter Image Sensor 251
7.2.1 Sensor Pixel 251
7.2.2 Global and Rolling Shutters 252
7.2.3 Challenges Facing Adoption of Global Shutter 254
7.2.4 CAAC-IGZO Image Sensor 255
7.3 Image Sensor Conducting High-Speed Continuous Image Capture 262
7.3.1 Overview 262
7.3.2 Conventional High-Speed Continuous-Capturing Image Sensor 263
7.3.3 High-Speed Continuous-Capturing CAAC-IGZO Image Sensor 263
7.3.4 Application to Optical Flow System 276
7.4 Motion Sensor 278
7.4.1 Overview 278
7.4.2 Configuration 278
7.4.3 Prototype 283
7.4.4 Sensor Pixel Threshold-Compensation Function 285
References 291
8 Future Applications/Developments 293
8.1 Introduction 293
8.2 RF Devices 294
8.2.1 Overview 294
8.2.2 NOSRAM Wireless IC Tag 294
8.2.3 Application Examples of NOSRAM Wireless IC Tags 298
8.3 X-Ray Detector 303
8.3.1 Outline 303
8.3.2 X-Ray Detection Principle 303
8.3.3 CAAC-IGZO X-Ray Detector 304
8.3.4 Fabrication Example and Evaluation 308
8.4 CODEC 310
8.4.1 Introduction 310
8.4.2 Encoder/Decoder 311
8.4.3 CAAC-IGZO CODEC 313
8.5 DC–DC Converters 314
8.5.1 Introduction 314
8.5.2 Non-hybrid DC–DC Converter 315
8.5.3 Fabricated CAAC-IGZO Bias Voltage Sampling Circuit with Amplifier 315
8.5.4 Evaluation Results of Fabricated CAAC-IGZO Bias Voltage Sampling Circuit with Amplifier 317
8.5.5 Proposed DC–DC Converter 318
8.6 Analog Programmable Devices 322
8.6.1 Overview 322
8.6.2 Design 322
8.6.3 Prototype 323
8.6.4 Possible Application to Phase-Locked Loop 330
8.7 Neural Networks 330
8.7.1 Introduction 330
8.7.2 Neural Networks 330
8.7.3 CAAC-IGZO Neural Network 332
8.7.4 Conclusion 334
8.8 Memory-Based Computing 335
8.9 Backtracking Programs with Power Gating 339
References 341
Appendix 343
Index 345
