Title Details

Liming Xiu earned his B.S. and M.S. degrees in physics from Tsinghua University, Beijing, China, in 1986 and 1988, respectively.  Mr. Xiu earned his second M.S. degree in electrical engineering from Texas A&M University, College Station, in 1995. Currently, he is involved in an IC design startup. He has 16 granted and 9 pending US patents and has published numerous IEEE journal papers and two books: VLSI Circuit Design Methodology Demystified (Wiley-IEEE Press) and Nanometer Frequency Synthesis beyond Phase-Locked Loop (Wiley-IEEE Press). He served as vice president of IEEE Circuit and Systems Society in years 2009-2010.

Foreword ix

Preface xi

Acknowledgment xvii

1 Importance of Clock Signal in Modern Microelectronic Systems 1

1.1 Clock Technology: One of the Four Fundamental Technologies in IC Design 1

1.2 Clock Signal Generator: The Knowledge-and-Skill Gap between Its Creator and Its User 3

1.3 How Is Sense-of-Time Created in Electrical World? 5

1.4 All Microelectronic Systems Are Frequency Driven 9

1.5 A New Kid in Town: The Clock Architect 14

References 15

2 Everything about the Clock 17

2.1 Clock Generation 17

2.2 Clock Distribution: Functional 18

2.3 Clock Distribution: Physical 19

2.4 Clock Usage: System Perspective 20

2.5 Clock Usage: Electrical Perspective 20

2.6 Clock Signal Quality 22

2.7 Clock Network Power Consumption 23

References 23

3 A Different Way of Constructing a Clock Signal: Time-Average-Frequency 27

3.1 Motivation 27

3.2 Clock Is Trigger and Gatekeeper: Essence of Stage-by-Stage Operation 30

3.3 Time-Average-Frequency: Brief Review 32

3.4 Circuit Architecture of Time-Average-Frequency Direct Period Synthesis 34

3.5 The Two Long-Lasting Problems: Small Frequency Granularity and Fast Frequency Switching 37

3.6 Time-Average-Frequency and “Jittery” Clock 40

3.7 Frequency Switching and Waveform Establishment in TAF-DPS Clock Generator 43

3.8 Allan Variance of TAF-DPS Clock Signal 43

3.9 Behavior of TAF Clock Signal under the Scope of Jitter 46

3.10 Spectrum of TAF Clock Signal 52

3.11 Impact of Implementation Imperfection 52

References 54

4 Time-Average-Frequency and Special Clocking Techniques: Gapped Clock Stretchable Clock and Pausible Clock 55

4.1 Gapped Clock and Synchronous FIFO 55

4.2 Stretchable Clock Pausible Clock and Asynchronous FIFO 59

4.3 Time-Average-Frequency Operation of Gapped Clock Stretchable Clock and Pausible Clock 61

References 65

5 Microelectronic System Design in the Field of Time-Average-Frequency: A Paradigm Shift 67

5.1 Digital Data Communication in the Field of Frequency 69

5.2 Data Transfer in Time-Average-Frequency Field: Transmitting Clock Available 72

5.3 Data Transfer in Time-Average-Frequency Field: Clockless Transmission 74

5.4 Clock Data Recovery in Time-Average-Frequency Field 76

5.5 Network-on-Chip GALS Strategy in Time-Average-Frequency Field 82

5.6 Network Time Synchronization in Time-Average-Frequency Field: Improved Time Granularity and Frequency Granularity 89

5.7 Crystalless Reference and Time-Average-Frequency Driven VLSI System: Source for Frequency Reference 93

5.8 Crystalless Reference and Time-Average-Frequency Driven VLSI System: Harmony in System-Level Design 96

5.9 Efficient Implementation of MCXO System in Time-Average-Frequency Field 97

5.10 CPU Throttling in Time-Average-Frequency Field 105

5.11 Spreading Clock Energy in Time-Average-Frequency Field 108

5.12 TAF-DPS as Circuit Technique in Building Special Function Blocks 114

5.12.1 TAF-DPS as DCO for PLL and DLL 114

5.12.2 TAF-DPS as Open-Loop Fractional Divider 117

5.12.3 TAF-DPS in Pulse Width Modulation 120

5.12.4 TAF-DPS for Message Transmission Using Spectrum 122

5.12.5 TAF-DPS for Message Transmission Using Duty Cycle 122

References 127

6 TAF-DPS Clock Generator and On-Chip Clock Distribution 131

6.1 Global Clock Distribution at Low Frequency 131

6.2 Resonant Clock Distribution Network Assisted by TAF-DPS 136

6.3 TAF-DPS Clock Source and FPGA 143

6.3.1 FPGA Operation and Flexibility 144

6.3.2 Prefabricated FPGA Structure and Clock/Frequency Distribution Requirement 144

6.3.3 Heterogeneous FPGA Computing and Frequency Requirement 145

6.3.4 Parallelism in FPGA and Frequency Requirement 145

6.3.5 TAF-DPS Clock Source and FPGA 145

6.3.6 Creating Clock Source of Sub-ppm Frequency Granularity and Two-Cycle Frequency Switching Speed with FPGA Custom Logic 146

References 147

7 Digital-to-Frequency Converter: A Component Enabling New Application Fields 149

8 Conclusion: Evolution of Timekeeper in Electrical World 155

Index 157